Moortec’s 7nm Embedded Temperature Sensor selected by Achronix to optimise performance and reliability in its 4th Generation Speedster FPGA
Moortec Semiconductor Ltd, providers of complete In-Chip PVT (Process, Voltage and Temperature) Monitoring Subsystems announced today that Achronix Semiconductor Corporation have chosen Moortec’s 7nm Embedded Temperature Sensor IP to optimise performance and increase reliability for the company’s Speedster®7t FPGAs.
Achronix specialise in high-performance FPGA solutions that include high-density FPGA ICs, eFPGA IP for ASIC and SoC designs, FPGA chiplets for multichip modules and SiPs (Systems in Packages), and accelerator boards for datacenter and HPC applications. Achronix also offers its best-in-class ACE tool suite, which supports all Achronix FPGA products. Achronix innovations in programmable logic set the industry standard for performance, power, and cost leadership.
Achronix’s new 7nm Speedster7t FPGA family offers up to 2.6M 6-input LUTS, 385 Mbits of embedded RAM, and up to 41K Int8 engines in the new MLP (Machine Learning Processor) blocks aimed at speeding AI/ML (Artificial Intelligence/Machine Learning) applications. The first device available is the 7t1500 and includes hardened interfaces to support up to eight ports of GDDR6 high bandwidth memory, four ports of 400G Ethernet, two ports of PCIe Gen5 and thirty two 112 Gbps SerDes ports.
“Achronix chose to use Moortec’s highly accurate 7nm embedded in-chip temperature sensor in our Speedster7t FPGA devices based on their accuracy and advanced features. Moortec’s in-chip temperature sensors enabled us to overcome a number of thermal challenges associated with advanced node design.” said Steve Mensor, Achronix’s VP of Marketing.
“We are delighted to be supporting Achronix as they continue to push FPGA technology boundaries with their latest generation Speedster product” said Moortec CEO Stephen Crosher.
“By working together, Moortec’s high accuracy and feature-rich embedded thermal sensing solution has helped Achronix to achieve high performance operation, especially when considering the high circuit density requirements for such advanced node FPGA solutions.”